This invention relates generally to integrated circuit operational amplifiers, and more particularly, to protecting inputs of an operational amplifier circuit having bipolar or junction field effect transistor inputs.
An operational amplifier (op amp) is a high gain electronic amplifier having its gain controlled by negative feedback. Op amps are utilized in most analog electronic circuits and have become a major building block in electronic systems having sensor interfaces, low pass, high pass or band pass filters; programmable gain amplifiers, instrumentation amplifiers, input isolation amplifiers for analog-to-digital converters, and output amplifiers for digital-to-analog converters. A more thorough description of operational amplifier topologies and specifications may be found in Microchip Technology Inc., application note AN722 which is incorporated by reference herein.
The input stage for an op amp includes a pair of differentially connected transistors that receive differential input signals and provide corresponding differential currents to an active load. The inputs of bipolar transistor or junction field effect transistor (JFET) op amps are connected to a transistor junction, rather than to an insulated gate as in metal oxide semiconductor (MOS) transistor technology. The bipolar or JFET type op amps can exhibit an undesirable characteristic known as phase reversal should either of the transistor junctions associated with the op amp inputs become forward biased. The transistor junctions become forward biased if the inputs thereto are above or below the voltage supply rails. If this condition should occur, a large reverse current flows (if a bipolar junction) and causes the op amp output to switch to an incorrect state.
The phase of the input signals is a relative term and is defined by the polarity of one signal with respect to the other signal. An op amp is in phase when the phases of the input signals and differential currents of the op amp are the same. Phase reversal of an op amp occurs when the phase of the differential currents is opposite the phase of the input signals. The amplifier operates over a Common Mode Range (CMR) of input signals that lie between the high and low supply voltages. In the case of a single-voltage to ground supply, the CMR includes one of the supply voltages, typically the low supply which is commonly ground reference potential. If one of the input signals is driven outside of the CMR due to noise or improper drive circuitry, the corresponding differential transistor will either turn off or form a forward biased parasitic diode. When the transistor junction forward biases, the phase of the differential currents reverses with respect to the phase of the input signals and may cause the op amp to malfunction and latch up (stop working).
Most bipolar and JET op amps have additional circuitry to protect against phase reversal. A pair of phase compensation diodes may be cross-couple connected between the differential inputs and the other differential transistors"" collectors to prevent phase reversal of the amplifier. When either one of the differential transistors"" collector-base junctions is forward biased, the corresponding cross-coupled diode conducts and prevents a phase reversal of the differential currents. However, this type of phase reversal prevention greatly increases the magnitudes of the differential currents, on the order of twenty to thirty times the normal current values. Although op amp failure is less likely to occur, these extremely high current levels can still cause the active load to malfunction and latch up the op amp.
These phase reversal protection diodes at the inputs of the op amp are supposed to conduct before the input diode junctions of the differential input transistors of the op amp, thus clamping the signal paths to maintain the correct output state. Therefore, the input diode junctions cannot be forward biased, thus no phase reversal. This solution is limited in that the clamping diodes must have a forward voltage drop of less than the input diode junctions of the differential input transistors of the op amp. A diode""s forward voltage is proportional to the natural log of the diode area, so the protection diodes may be quite large in area on the silicone substrate because an allowance of some margin for a smaller diode forward voltage than the input differential pair must be used. This requirement for the protection diodes forward voltage drop and increased area requirements may require additional processing steps in the fabrication of the op amp, or changes to the input differential transistor pair of the op amp.
It may also limit the amount of forward current that the op amp input can handle before phase reversal may occur. Conduction or turn on of the protection diodes is relatively gradual and varies significantly with temperature, thus making the clamping threshold of these diodes imprecise.
Referring to FIG. 1, a prior art schematic diagram of an operational amplifier input stage having diode phase reversal protection is illustrated. A typical single power supply (ground and a positive voltage) input stage of a bipolar transistor integrated circuit operational amplifier (op amp) is generally indicated by the numeral 100. One skilled in the art of analog integrated circuits would also recognize replacement of the bipolar transistors with junction field effect transistors, also contemplated herein and within the scope of the present invention.
The op amp input stage 100 includes cross-coupled phase compensation diodes for preventing phase reversal, and current compensation diodes for preventing overshoot of the differential currents. A pair of differentially connected transistors 102 and 104, which can be either bipolar or junction field effect transistors (JFETs), have their current circuits connected together on one side to divide the output of a current source 106. As used herein, a transistor""s xe2x80x9ccurrent circuitxe2x80x9d refers to the collector-emitter circuit of a bipolar transistor, or the source-drain circuit of a JFET; a transistor""s xe2x80x9ccontrol circuitxe2x80x9d refers to the base of a bipolar device, or the gate of an JFET. In the circuit illustrated in FIG. 1, the differential transistors are bipolar pnp transistors.
Input terminals 108 and 110 are adapted to receive differential input signals through series resistors 112 and 114. In the manner characteristic of differential amplifiers, the transistors 102 and 104 divide the current from the current source 106 in mutual opposition, with the amount of current through each of the transistors 102 and 104 varying according to the relative input voltage signals applied to their bases from the input terminals 108 and 110, respectively. If a constant, known bias is applied to one of the input transistor bases, the magnitude of the signal at the base of the other input transistor can be determined by the amount of current flowing through that transistor.
The input current source 106 operates from a positive voltage supply, VCC, while the collectors of the pnp input transistors 102 and 104 are connected to a negative voltage supply Vxe2x88x92 (preferably ground potential) through respective series-connected first and second trimmable input resistors 116 and 118. The trimmable resistors 116 and 118 may be used to minimize any offset voltage of the input circuit.
The input stage includes a folded cascode pair of active load npn bipolar transistors 120 and 122, whose emitters are connected to the collectors of input transistors 104 and 102, respectively. The bases of transistors 120 and 122 are connected together for common biasing. A bias circuit for the transistors 120 and 122 consists of a current source 124 that is connected to the bases of the transistors 120 and 122 and to a diode 126, which is connected through resistor 128 to ground potential. Diode 128 can be a diode-connected transistor. The magnitudes and relative phase of the currents flowing through the current circuits of transistors 120 and 122 are controlled by the base-emitter voltages, which are determined by the bias voltages at their bases and by the voltages across resistors 116 and 118. The base-emitter voltages control the bias current for the transistors 120 and 122.
The active load is formed by a pair of pnp transistors 130 and 132, whose emitters are connected to VCC through resistors 134 and 136, respectively, and whose bases are connected together for common biasing. The transistor 130 base and collector are connected to the transistor 120 collector, and the transistor 132 collector is connected to the transistor 122 collector. The output current to the second stage (not illustrated) of the op amp is taken at the collector of transistor 132. The transistors 130 and 132 are connected as a current mirror, with the current through transistor 132 mirroring that through transistor 130. Any imbalance in the input signals at inputs 108 and 110 causes an imbalance in the currents through the transistors 120 and 122. The output current to the second stage reconciles the equal currents through transistors 130 and 132 with any current imbalance between transistors 120 and 122. As the input signal at the input 108 or 110 is decreased relative to the other input signal, the respectively connected transistor 102 or 104 collector current increases, which causes the respective resistor voltage to increase. However, if one of the input voltages at input 108 or 110 falls more than a diode drop below the voltage across respective resistor 116 or 118, the collector-base pn junction of its respective input transistor 102 or 104 becomes forward biased. This creates a parasitic diode 138 or 140 that reverses the current flow through the collector-base junction, which decreases the voltage across resistor 116 or 118 and reverses the phase of the cascode transistors 102 and 104 currents such that the amplifier is phase reversed. As one of the differential inputs 108 or 110 is decreased, the respective resistor voltage should increase, but the existence of the forward biased parasitic diode causes the resistor voltage to decrease instead and results in phase reversal of the amplifier. For bipolar differential transistors, the input stage is typically biased so that phase reversal occurs at input signals outside the common mode rejection voltage (CMR) and below the low reference potential. For example, if the resistor voltages are biased to 80 mV, the junction will forward bias for an input of approximately xe2x88x92400 mV at room temperature. However, if the resistor voltages increase, it is possible that phase reversal can occur for input signals inside the CMR.
A pair of phase compensation diodes 142 and 144 are cross-coupled between the bases and collectors of the transistors 102 and 104 to prevent phase reversal of the currents flowing through the transistors 120 and 122. When one input is driven more than a diode drop below the corresponding resistor 116 or 118 voltage, the cross-coupled diode 142 or 144 connected to that input 108 or 110 conducts and reduces the voltage across the other resistor 118 or 116 to a smaller value to prevent phase reversal of the resistor voltages, and thus phase reversal of the currents in transistors 120 and 122. For the same voltage, the phase compensation diodes 142 and 144 conduct more current than the parasitic diodes 138 and 140 of the differential transistors 102 and 104, thus preventing phase reversal. In normal operation, the phase compensation diodes 142 and 144 are reverse biased and have no effect on the input circuit.
The circuit illustrated in FIG. 1 and described above is a conventional bipolar differential input op amp. While the operational amplifier 100 avoids phase reversal problems, the effect of forward biasing one of the parasitic diodes 138 or 140, and activating one of the cross-coupled diodes 142 or 144 is to reduce the voltages across the resistors 116 and 118 in response to the differential transistor""s forward biased collector-base junction and the cross-coupled diode. Thus, the base-emitter voltages across the cascode transistors 120 and 122, and hence their bias currents increase so that their currents increase exponentially, on the order of twenty to thirty times their normal levels. These much higher current levels can cause the active load to malfunction and latch up the op amp.
Therefore, what is needed is a circuit to protect the bipolar or JFET transistor inputs so as to prevent phase reversal of the op amp without greatly increasing current levels in the integrated circuit op amp, and preferably to use a standard complementary metal oxide semiconductor (CMOS) process to fabricate the protection circuits thereof.
The invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing, in an integrated circuit bipolar or JFET op amp, protection from output phase reversal from a forward biased collector-base parasitic pn diode of the input amplifier transistor and without having to rely upon input clamping diodes. In the present invention, at least two comparators are used to compare the op amp differential input voltages to a voltage reference (ground and/or power supply voltage(s)). P-channel metal oxide semiconductor (PMOS) transistors may be used for the differential pair of the comparator because a PMOS differential pair configuration includes ground in its common mode voltage range.
These comparators have an intentional mismatch so that the comparator switch point may be adjusted below ground, but above the point where the op amp input diode junctions become forward biased. Preferably, this mismatch may be constructed by making the input transistor width to length (W/L) ratios different from each other. As the input is lowered below the switch point of the comparator, its output toggles to clamp the signal paths within the op amp so as to maintain the correct output phase state of the op amp.
It is also contemplated and within the scope of the present invention that N-channel metal oxide semiconductor (NMOS) transistors may be used to include supply voltage, VDD, in its common mode voltage range. In this embodiment, the comparators of the present invention use NMOS transistors for the differential pair so that VDD is included in the common-mode range of the comparator.
In another embodiment of the invention, both PMOS and NMOS transistors are used for the differential pairs in comparators that simultaneously compare the differential input signals to both VSS (low supply or ground) and VDD. If the input voltage should rise above VDD or below ground, the respective comparator toggles to clamp the internal op amp signal paths to maintain the correct output phase state of the op amp.
A feature of the present invention is that a pair of comparators are used to monitor signal voltages on the differential inputs of a bipolar or JFET input op amp and prevent output phase reversal if these input signals go outside of a desired range.
Another feature of the present invention is monitoring the op amp differential inputs for signals below the negative voltage or common ground reference of the power supply to the op amp by using a pair of PMOS comparators.
Still another feature of the present invention is monitoring the op amp differential inputs for signals above the positive voltage reference of the power supply to the op amp by using a pair of NMOS comparators.
Yet another feature of the present invention is monitoring the op amp differential inputs for signals below the negative voltage or common ground reference and above the positive voltage reference of the power supply to the op amp by using a pair of PMOS comparators and a pair of NMOS comparators, respectively.
Still another feature is setting the clamping voltage setpoint by adjusting the mismatch (offset) of the comparator by making the input transistor W/L ratios different from each other.
An advantage of the present invention is that the phase reversal protection comparators may be fabricated with a standard CMOS process.
Another advantage of the present invention is that its phase reversal clamp voltage is more precise than that of a simple diode circuit.
Still another advantage is that the clamping voltage is less sensitive to temperature and process variations, thus operation of the op amp is more robust.
Yet another advantage is that the input comparators of the present invention are smaller than phase reversal diodes and thus require less area on the integrated circuit die.